• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor, and more particularly to a trench gate MOS transistor, comprising: a first conductive semiconductor substrate having trenches having a predetermined width and a predetermined depth; A high concentration first conductivity type impurity region formed near the bottom of the trench; A second conductivity type body region formed on the first conductivity type semiconductor substrate to be shallower than the trench depth; A high concentration first conductivity type source region formed near the surface of the semiconductor substrate on the body region so as to contact the trench; A gate oxide layer including a portion of the trench surface and a portion of the source region; And a gate electrode layer formed in the trench coated with the gate oxide film.
    公开号:KR19980055020A
    申请号:KR1019960074226
    申请日:1996-12-27
    公开日:1998-09-25
    发明作者:김한수
    申请人:김광호；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Trench gate type MOS transistor and its manufacturing method
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to MOS transistors, and more particularly to trench gate type MOS transistors.
    Trenchgate type transistors are used in a wide variety of applications, from low power devices to high power devices. Recently, low-voltage trench gate morph transistors have been developed that greatly reduce ON resistance. This device has the lowest on-resistance characteristics of conventional MOS transistors and is ideally close to the resistance a silicon device can have.
    The resistance generated in the trench gate type MOS transistor is divided into channel resistance, epi layer resistance, and accumulation layer resistance. Because of the high cell density, the trench structure has a smaller channel resistance than the conventional planar structure, and the epi layer is thin, so the epi layer resistance is small. However, the accumulation layer resistance at the trench bottom has the same value as the existing planar structure.
    SUMMARY OF THE INVENTION An object of the present invention is to provide a trench gate type mosistor and a method of manufacturing the same, which minimize the on-resistance by reducing the accumulation layer resistance of the trench gate type mosistor in order to solve the problems of the related art.
    In order to achieve the above object, a trench gate type morph transistor according to the present invention comprises a first conductive semiconductor substrate having a trench formed in a predetermined width and a predetermined depth; A high concentration first conductivity type impurity region formed near the bottom of the trench; A second conductivity type body region formed on the first conductivity type semiconductor substrate to be shallower than the trench depth; A high concentration first conductivity type source region formed near the surface of the semiconductor substrate on the body region so as to contact the trench; A gate oxide layer including a portion of the trench surface and a portion of the source region; And a gate electrode layer formed in the trench coated with the gate oxide film.
    In order to achieve the above object, a method of manufacturing a trench gate type morph transistor according to the present invention comprises the steps of: forming a second conductivity type impurity region and trench on a first conductivity type semiconductor substrate; Forming a gate oxide film on a surface of the trench on which the trench is formed; And injecting a high concentration of a first conductivity type impurity into a portion of the trench bottom and the second conductivity type impurity region adjacent to the trench.
    1 is a view showing a trench gate type morph transistor according to the prior art.
    2 is a view illustrating a trench gate type morph transistor according to an embodiment of the present invention.
    Explanation of symbols on the main parts of the drawings
    10: N-type semiconductor substrate 15: high concentration N-type impurity region
    20: P-type body region 30: high concentration N-type source region
    40: gate oxide film 50: polysilicon gate
    Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
    In the trench-gate type morph transistor, carriers are accumulated on the oxide film 40 interface at the bottom of the trench to form a path through which current is conducted. The carriers gathered in the accumulation layer have a very thin thickness and thus have a high resistance value (see FIG. 1).
    When the high concentration N-type impurity region 15 is formed by injecting a high concentration N-type impurity into the trench bottom as illustrated in FIG. Can be.
    The manufacturing process of the trench gate type morph transistor according to the present invention is as follows. P-type impurity regions 20 and trenches are formed on the N-type semiconductor substrate 10. A gate oxide film 40 is formed on the surface of the semiconductor substrate on which the trench is formed. High concentration N-type impurities are implanted into the trench bottom and the portion of the P-type impurity region 20 adjacent to the trench. As a result, the high concentration N-type impurity region 15 near the source region 30 and the trench bottom is simultaneously formed. Using this method, it is possible to form a high concentration N-type impurity region 15 near the trench bottom without using an additional mask pattern.
    The present invention can minimize the on-resistance of the device by reducing the accumulation layer resistance near the trench bottom.
    权利要求:
    Claims (2)
    [1" claim-type="Currently amended] A first conductive semiconductor substrate having trenches having a predetermined width and a predetermined depth; A high concentration first conductivity type impurity region formed near the bottom of the trench; A second conductivity type body region formed on the first conductivity type semiconductor substrate to be shallower than the trench depth; A high concentration first conductivity type source region formed near the surface of the semiconductor substrate on the body region so as to contact the trench; A gate oxide layer including a portion of the trench surface and a portion of the source region; And a gate electrode layer formed in the trench coated with the gate oxide film.
    [2" claim-type="Currently amended] Forming a second conductivity type impurity region and a trench on the first conductivity type semiconductor substrate; Forming a gate oxide film on a surface of the trench on which the trench is formed; And implanting a high concentration of a first conductivity type impurity into a portion of the trench bottom and the second conductivity type impurity region adjacent to the trench.
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    同族专利:
    公开号 | 公开日
    KR100521994B1|2005-12-21|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-27|Application filed by 김광호, 삼성전자 주식회사
    1996-12-27|Priority to KR1019960074226A
    1998-09-25|Publication of KR19980055020A
    2005-12-21|Application granted
    2005-12-21|Publication of KR100521994B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960074226A|KR100521994B1|1996-12-27|1996-12-27|Trench gate type MOS transistor and its manufacturing method|
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